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[VHDL-FPGA-Verilog] uart_verilog

Description: 包含UART口的VERILOG源程序，该程序在FPGA上验证通过，可作为芯片设计，或FPGA设计的一个完整IP核，硬件设计的兄弟们可参考一下。-include UART port of VERILOG source, the program tested in FPGA, as chip design, or FPGA design of a complete IP cores, hardware design brothers can make reference.
Platform: | Size: 9216 | Author: 施向东 | Hits:

[VHDL-FPGA-Verilog] 数字频率计实验报告

Description: 课程设计要求设计并用FPGA实现一个数字频率计，具体设计要求如下： 测量频率范围： 10Hz～100KHz 精度： ΔF / F ≤ ±2 % 系统外部时钟： 1024Hz 测量波形： 方波 Vp-p ＝ 3～5 V 硬件设备：Altera Flex10K10 五位数码管 LED发光二极管 编程语言：Verilog HDL / VHDL-curriculum design and FPGA design to achieve a digital frequency meter, the specific design requirements are as follows : measurement frequency range : 10Hz to 100KHz precision : F/F 2% external clock system : 1024Hz Waveform Measurement : square Vp-p = 3 ~ 5 V hardware : Altera Flex10K10 five digital LED light emitting diode programming languages : Verilog HDL/VHDL
Platform: | Size: 144384 | Author: 兰 | Hits:

[DSP program] 电子线路实验报告

Description: 设计一数字 频率计，其技术要求如下： (1) 测量频率范围：1Hz~100kHz。 (2) 准确度Dfx/fx£ ± 2%。 (3) 测量信号：方波，峰峰值为3V~5V。-design a figure frequency meter, the technical requirements are as follows : (a) measuring frequency range : 1Hz- 100kHz. (2) the accuracy Dfx/fxpound 2%. (3) Measurement of signal : square wave peak to peak for 3V to 5V.
Platform: | Size: 86016 | Author: 兰 | Hits:

[VHDL-FPGA-Verilog] 用modelsim仿真一个正弦波产生程序

Description: 用modelsim仿真一个正弦波产生程序-modelsim simulation using a sine wave generated procedures
Platform: | Size: 68608 | Author: 阿乐 | Hits:

[VHDL-FPGA-Verilog] manchester_verilog

Description: 这时manchesite编码，VERILOG语言，VHDL的找本站我发的帖子-manchesite time coding, VERILOG language, VHDL I find a site in a posting
Platform: | Size: 9216 | Author: 李无志 | Hits:

[Communication] 基于USB-ATA接口的海量存储器的设计与实现

Description: 介绍了一种基于通用可编程接口的通用串行总线-高级技术配件解决方案，将普通硬盘转化为Usb Mass Storage.-introduces a general programmable interface based on the Universal Serial Bus-senior technical accessories solution that will drive into ordinary Usb Mass Storage.
Platform: | Size: 86016 | Author: 蔡明 | Hits:

[VHDL-FPGA-Verilog] two_d_dct_serial

Description: altera公司提供的适用于包涵DSP内核的FPGA的二维DCT变换源码，语言是：verilog 性能不错，不过资源消耗有点大，可以用来学习多项式变换的DCT算法-ALTERA companies covered in the application of FPGA DSP core 2D DCT source language is : Verilog performance is good, but a bit large consumption of resources can be used to transform learning polynomial algorithm DCT
Platform: | Size: 24576 | Author: 猪猪 | Hits:

[VHDL-FPGA-Verilog] 数据结构c描述习题集答案

Description: 减1计数器 一、设计要求 用Verilog HDL语言设计一个计数器。 要求计数器具有异步置位/复位功能，可以进行自增和自减计数，其计数周期为2^N（N为二进制位数）。 二、设计原理 输入/输出说明： d：异步置数数据输入； q：当前计数器数据输出； clock：时钟脉冲； count_en：计数器计数使能控制（1：计数/0：停止计数）； updown：计数器进行自加/自减运算控制（1：自加/0：自减）； load_d-a counter a reduction, design requirements using Verilog HDL design of a counter. Asynchronous requests with counter-home/reset functions can be carried out by self and self-count reduction, cycle counting of 2 ^ N (N for binary digit). Second, the principle of design input/output Description : d : asynchronous home several data input; Q : The current counter data output; Clock : clock pulse; Count_en : Counting enable control (1 : Counting/0 : Stop counting); Updown : dollars several self-Canada/reduction Operational control (1 : Since the plus/0 : Since decrease); load_d
Platform: | Size: 111616 | Author: tutu | Hits:

[Other] ldpc理论

Description: 一篇LDPC编码的论文，具有很好的参考价值-A thiese about ldpc code, It has a good value.
Platform: | Size: 3634176 | Author: john | Hits:

[Embeded-SCM Develop] verilog_code

Description: 這是一堆verilog的source code.包含許多常用的小電路.還不錯用.-many verilog source codes, include a lot of small electrocircuit.
Platform: | Size: 169984 | Author: ㄚ福 | Hits:

[CSharp] OS课题设计

Description: 任务 设计一个虚拟存储区和内存工作区，并使用下述算法计算访问命中率。 （1）先进先出的算法（FIFO） （2）最近最少使用算法（LRU） （3）最佳淘汰算法（OPT） （4）最少访问页面算法（LFU） （5）最近最不经常使用算法（NUR） 命中率=（1 – 页面失效次数）/页地址流长度-mission design a virtual memory storage area and the work area and to use the following algorithm to visit the hit rate. (1) FIFO algorithm (FIFO) (2) at least recently used algorithm (LRU) (3) eliminated the best algorithm (OPT) (4) at least visit pages algorithm (LFU) (5) most recently used algorithm (NUR) life China rate = (1-pages failure number)/page-length addre
Platform: | Size: 2048 | Author: 东方少秋 | Hits:

[Other Embeded program] sap1

Description: 這是用verilog寫的一個簡單的處理器，雖然只具有5個指令，但是可以透過這個範例，來了解到cpu的架構，與如何開發處理器，相信會有很大的啟發。-using Verilog This is a simple written by the processor, although with only five directives, through this example, to understand cpu architecture, how to develop processor, it would be very enlightening.
Platform: | Size: 33792 | Author: 吳中億 | Hits:

[VHDL-FPGA-Verilog] arbit

Description: verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
Platform: | Size: 5120 | Author: 宋昆仑 | Hits:

[VHDL-FPGA-Verilog] bidir

Description: verilog 代码. 经验证成功,可以作为标准单元库,为FPGA设计者使用.-Verilog code. Certified success, as a standard cell library for the use of FPGA designers.
Platform: | Size: 4096 | Author: 宋昆仑 | Hits:

[Crack Hack] AES算法

Description: 一个非常好的ASE代码，通过实验证明能编译通过-A perfect AES program code, and it can be run after translation and edition.
Platform: | Size: 209920 | Author: 张力 | Hits:

[ARM-PowerPC-ColdFire-MIPS] signal_cpu_sort

Description: Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_MEMORY, REGISTER, PC, and TESTBRANCH.-Use the verilog language write a MIPS CPU code, and have additional instruction, for example: selection sort instruction. The code has contain combination circuit and sequenial circuit. CPU have contain ALU, ADD, ALU_CONTROL, DATA_MEMORY, INST_MEMORY, REGISTER, PC, and TESTBRANCH.
Platform: | Size: 8192 | Author: 張大小 | Hits:

[CSharp] cccp

Description: des-soft.com/download/soft/3894.htm - 12k - 网页快照 - 类似网页 - 以Verilog 描述DES 加密算法(电子书)[ 繁体 ] ... CISCO 的fireware, router , SONY 的PS2 的都一再的证明了这个事实. 现在, 我们 就以著名的网络安全加密算法DES 为例子, 来看看如何用Verilog 来表达... ... Re: 以Verilog 描述DES 加密算法(电子书) 由Anonymous 发表于2002/08/29,Thu @15:46:38 ... www.icdiy.org/article.php3?sid=18 - 19k - 网页快照 - 类似网页 -des-soft.com/download/soft/3894.htm- 12k-web snapshot-like web-to Verilog description DES encryption algorithm (e-books) [traditional] ... the fireware CISCO, router, Sony's PS2 has repeatedly proved the this fact. now, we have a well-known network security DES encryption algorithm for example, to see how to use Verilog expression ... ... Re : Verilog description DES encryption algorithm (e-books) from Anonymous on 2002/08/29, Thu @ 15 : 46-38 ... www.icdiy.org/article.php3 sid = 18-19k-web snapshot-like web
Platform: | Size: 8192 | Author: le | Hits:

[VHDL-FPGA-Verilog] ZBT SRAM控制器参考设计_verilog_xilinx

Description: ZBT SRAM控制器参考设计，xilinx提供，（ZBT SRAM是一种高速同步SRAM）-ZBT SRAM controller reference design for Xilinx (ZBT SRAM, a high-speed synchronous SRAM)
Platform: | Size: 35840 | Author: 陈旭 | Hits:

[VHDL-FPGA-Verilog] 8位大小比较器

Description: 8位大小比较器的VHDL源代码，Magnitude Comparator VHDL description of a 4-bit magnitude comparator with expansion inputs-eight compared with the size of the VHDL source code, Magnitude Comparator VHDL description of a 4-bit magnitude comparator inputs with expansion
Platform: | Size: 1024 | Author: 蔡孟颖 | Hits:

[source in ebook] SystemC片上系统设计源代码

Description: SystemC片上系统设计的源代码： 书籍介绍： SystemC是被实践证明的优秀的系统设计描述语言，它能够完成从系统到门级、从软件到硬件、从设计到验证的全部描述。SystemC 2.01已作为一个稳定的版本提交到IEEE，申请国际标准。 本书为配合清华大学电子工程系SystemC相关课程的教学而编写。全书分9章，内容包括：硬件描述语言的发展史；SystemC出现的历史背景和片上系统设计方法学概述；SystemC的基本语法；SystemC的寄存器传输级设计和SystemC的可综合语言子集，以及根据作者设计经历归结的RTL设计准则和经验；接口、端口和通道等SystemC行为建模实例——片上总线系统；SystemC与VHDL/Verilog HDL的比较；SystemC的验证标准和验证方法学；SystemC开发工具SystemC_win、WaveViewer等，以及使用MATLAB进行SystemC算法模块的验证。每一章都精心编写了课后习题以配合教学的需要。 本书可作为大学电子设计自动化（EDA）相关课程教材，也可供电子工程技术人员作为SystemC设计、应用开发的技术参考书。本书丰富的实例源代码特别适合初学者根据内容实际运行、体会，举一反三，以掌握SystemC进行应用系统设计。 -SystemC system on chip design source : books introduced : SystemC has been proven in practice is an excellent system design description language, it can be completed from the system level to the door, from hardware to software, from design to verification of all description. SystemC has 2.01 as a stable version submitted to the IEEE, the application of international standards. The book to tie in electronic engineering at Tsinghua University SystemC related courses and preparation of teaching. Book nine chapters, including : hardware description language development history; SystemC is the historical background and system-on-chip design methodology outlined; SystemC basic grammar; SystemC register-transfer-level design and synthesis of SystemC language subset, as well as design experience b
Platform: | Size: 2640896 | Author: c.li | Hits:
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